The realization of a synaptic element is of interest for hardware implementation of deep learning networks. Weights are modified and stored by modulating the conductivity of non-volatile memory array elements. Use of the adjustable channel conductance of ferroelectric (FE) field-effect transistors (FETs) FE-FETs as a synaptic weight date back to the early 1990s. See H. Ishiwara, “Proposal of Adaptive-Learning Neuron Circuits with Ferroelectric Analog-Memory Weights,” Jpn. J. Appl. Phys. 32, 442-446 (January 1993).
Significant progress has been made using perovskite ferroelectrics such as Pb(Zr,Ti)O3. See, for example, Kaneko et al., “Ferroelectric Artificial Synapses for Recognition of a Multishaded Image,” IEEE Transactions on Electron Devices, vol. 61, Issue 8 (August 2014). However, implementation on a silicon complementary metal-oxide-semiconductor (CMOS) platform remains challenging due to incompatibilities of perovskite ferroelectrics with CMOS processing, e.g., due to the need for thick films and hydrogen barriers, thermal budgets that are incompatible with the CMOS back-end, and contamination risks posed by lead-containing perovskites.
Thus, techniques for implementing ferroelectric artificial synaptic devices in the CMOS back-end within the BEOL thermal budget limitations, and in a way that does not require thick films or hydrogen barriers, and which pose no undue contamination risks would be desirable.